1. Field of the Invention
The present invention relates to a method for designing a semiconductor integrated circuit having a power control transistor and configured to achieve a power control for low power consumption.
2. Description of the Related Art
Conventionally, as a method for achieving low power consumption of a semiconductor integrated circuit, there is a known method which employs a zigzag super cut-off CMOS circuit (ZSCCMOS) or a zigzag boosted gate MOS circuit (ZBGMOS).
FIG. 14 shows a configuration of the ZSCCMOS circuit. The ZSCCMOS circuit has a combinational circuit 50 for which power is cut off. In the combinational circuit 50, a logic gate circuit which outputs “L” immediately before power cut-off has a high-potential power supply end connected to a pseudo-power supply line VDDV connected via a power control transistor MP to a high potential power supply line VDD, and a low potential power supply end connected to a low potential power supply line VSS. Also, a logic gate circuit which outputs “H” immediately before power cut-off has a high-potential power supply end connected to the high potential power supply line VDD, and a low potential power supply end connected to another pseudo-power supply line VSSV connected via a power control transistor MN to the low potential power supply line VSS.
With the circuit configuration, the gate-drain breakdown voltage of the power control transistor can be suppressed to a low value, and the state recovery time of the combinational circuit 50 during recovery of power can be reduced (see Japanese Unexamined Patent Application Publication No. 2005-39334 and Kyeong-sik Min et al., “Zigzag Super Cut-off CMOS (ZSCCMOS) Block Activation with Self-Adaptive Voltage Level Controller: An Alternative to Clock-Gating Scheme in Leakage Dominant Era”, 2003 IEEE International Solid-State Circuits Conference, session 22, TD: Embedded Technologies, Paper 22.8).
However, semiconductor integrated circuits employing the above-described low power consumption circuit technique have the following problem.
A net list which is generated in a logic design stage does not have information about connection of the high-potential power supply end or low potential power supply end of each primitive logic gate in a circuit for which power is to be cut off. Therefore, the layout of the semiconductor integrated circuit employing the low power consumption circuit technique cannot be designed directly from the net list.
Also, in the semiconductor integrated circuit employing the low power consumption circuit technique, even the same primitive logic gate has different connection destinations of the high-potential power supply end and the low potential power supply end, depending on whether the output state during power cut-off is “H” or “L”. Therefore, during layout design, wiring of the power supply ends cannot be automatically achieved using currently commonly used layout cells and layout tools. Also, when the wiring of the power supply ends is manually performed, it takes a very long time, which is impractical.
Note that, as a method for designing a layout for providing multiple power supplies, Japanese Unexamined Patent Application Publication No. 2003-218210 discloses a layout designing method for arranging layout cells, where an internal power supply is electrically separated from a main line power supply, and selectively wiring power supplies in a wiring step. However, this method requires a special process in the wiring step, and therefore, when the number of logic gates to be laid out is huge, a very long processing time is disadvantageously required.